Field of the Invention
The present invention relates to a semiconductor package including a semiconductor device mounted on a package board.
Description of the Related Art
The structure of a semiconductor package including a semiconductor device will be described below. First, the structure of the semiconductor device will be described below. FIG. 1 of the accompanying drawings is a block diagram showing a structural example of semiconductor device 10 according to the related art. It is assumed that semiconductor device 10 is a DRAM (Dynamic Random Access Memory).
As shown in FIG. 1, semiconductor device 10 includes a plurality of memory cell blocks 20-1 through 20-n (n represents an integer which is 1 or greater) each including a plurality of memory elements, CA pad array 31 including a plurality of terminals to which address signals and command signals are input from an external source, DQ pad array 32 including a plurality of terminals which send data to and receive data from an external source, column decoder 41 and row decoder 42 for specifying a memory element according to an address signal, and data input/output control circuit 45 for controlling the inputting and outputting of data.
An address signal is a signal for specifying either one of the memory elements. A command signal is a signal for indicating the writing of data into or the reading of data from the memory elements.
CA pad array 31 includes command signal pads to which command signals are input from the external source and address signal pads to which address signals are input from the external source. The address signal pads and the command signal pads will be hereinafter collectively referred to as signal pads.
DQ pad array 32 includes a plurality of data pads which send and receive data. Each of CA pad array 31 and DQ pad array 32 includes a power supply voltage pad to which a power supply voltage (Vdd) is applied from an external source and a ground potential pad to which a ground potential (Vss or Gnd) is applied from an external source. The power supply voltage pad will be hereinafter referred to as a Vdd pad, and the ground potential pad as a Vss pad.
In FIG. 1, a receiver circuit for amplifying signals input from an external source and an input/output circuit for amplifying data which are sent to and received from an external source are omitted from illustration.
FIG. 2 of the accompanying drawings is a cross-sectional view showing a structural example of a semiconductor package including the semiconductor device shown in FIG. 1.
As shown in FIG. 2, semiconductor device 10 is mounted on package board 50 and covered with resin body 56. Pads 200 disposed on the upper surface of semiconductor device 10 are connected to bond fingers 210 on package board 50 by bonding wires (hereinafter simply referred to as “wires”) 220. Pads 200 are one type of the pads included in CA pad array 31 or DQ pad array 32. Bond fingers 210 are one type of electrically conductive pads which are electrically connected to pads 200 on semiconductor device 10 by wires 220, and are connected to solder balls 51 by interconnects 52 and via plugs 54.
Of interconnects 52 disposed on package board 50, the interconnects connected to the command signal pads of CA pad array 31 are referred to as command interconnects, the interconnects connected to the address signal pads of CA pad array 31 as address interconnects, and the interconnects connected to the data pads of DQ pad array 32 as data interconnects.
An example of stacked semiconductor package which is of a PoP (Package on Package) structure with a plurality of semiconductor devices mounted on a printed wiring board is disclosed in JP 2009-38142A. An example of technology relative to a redistribution layer (RDL) referred to in JP 2009-38142A is disclosed in JP 2005-123291A.
FIG. 3 of the accompanying drawings is a plan view showing connections between pads on a semiconductor device and bond fingers on a package board. FIG. 3 shows a portion of CA pad array 31.
As shown in FIG. 3, bond fingers 211 through 216 are disposed on package board 50 in a vertical array as shown. Vdd pad 201, address signal pads 202 through 205, and Vss pad 206 are disposed on semiconductor device 10 parallel to the pad array of bond fingers 211 through 216.
“V” noted on Vdd pad 201 and bond finger 211 indicates that they are the pad and the bond finger to which Vdd is applied. “G” noted on Vss pad 206 and bond finger 216 indicates that they are the pad and the bond finger to which Vss is applied. “A1” through “A4” noted on address signal pads 202 through 205 and bond fingers 211 through 215 indicate that they are the pads and the bond fingers to which address signals A1 through A4 are transmitted.
Each of address signal pads 202 through 205 is connected through interconnects to amplifiers in the receiver circuit.
In FIG. 3, only address signal pads for address signals A1 through A4 are illustrated, and address signal pads for address signals other than address signals A1 through A4 and command signal pads are omitted from illustration. For example, address signal pads (not shown) for address signals other than address signals A1 through A4 and command signal pads (not shown) are disposed below Vss pad 206 shown in FIG. 3.
Vdd pad 201, address signal pads 202 through 205, and Vss pad 206 are arranged in a single array at a spaced interval between adjacent ones thereof. Bond fingers 211 through 216 are disposed at respective vertical positions aligned with Vdd pad 201, address signal pads 202 through 205, and Vss pad 206, respectively. Vdd pad 201 and bond finger 211 are connected to each other by wire 221. Vss pad 206 and bond finger 216 are connected to each other by wire 226. Address signal pads 202 through 205 are connected to respective bond fingers 212 through 215 by respective wires 222 through 225.
In one array of pads, the ratio of the number of successive signal pads to a Vss pad or a Vdd pad is defined as “SG ratio” which means the ratio between signals and ground (or power supply). In the structural example shown in FIG. 3, since there is one Vdd pad or Vss pad for four address signal pads, the SG ratio is 4:1. The SG ratio of the numbers of bond fingers which connect these pads to the bond fingers is also 4:1. The SG ratio is similarly defined for address signal pads and wires which are not illustrated.
According to the PoP structure, the command interconnects and the address interconnects often extend longer parallel to the principal surface of package board 50 than the data interconnects due to the interconnect density and interconnect limitations. Furthermore, since each of wires 221 through 226 shown in FIG. 3 has a parasitic inductance as shown in FIG. 4 of the accompanying drawings, and the SG ratio of the CA pad array is 4:1 as described above with reference to FIG. 3, which is smaller than the SG ratio of the DQ pad array, the wires have a low power feeding capability and each develop a parasitic inductance between itself and an adjacent wire. As the loop inductance between S (signal) and G (ground) wires is large, the wires are subject to large noise and jitter.
According to the LPDDR2 (Low Power Double Data Rate 2) standards, since address interconnects transfer signals at a double rate, it is important to reduce such noise and jitter for better signal quality.